[RISCV] Add SimplifyDemandedBits and hasAllNBitUsers support for CLSW.#174542
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[RISCV] Add SimplifyDemandedBits and hasAllNBitUsers support for CLSW.#174542
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This matches what we do for CLZW and other W instructions.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThis matches what we do for CLZW and other W instructions. Full diff: https://github.com/llvm/llvm-project/pull/174542.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index e2d6d37d8f6e3..b51ed9cddbeb2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -4085,6 +4085,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
case RISCV::ROLW:
case RISCV::RORW:
case RISCV::RORIW:
+ case RISCV::CLSW:
case RISCV::CLZW:
case RISCV::CTZW:
case RISCV::CPOPW:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 1ebc7235a74e5..363efd5e0a3dc 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20909,6 +20909,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
break;
}
case RISCVISD::ABSW:
+ case RISCVISD::CLSW:
case RISCVISD::CLZW:
case RISCVISD::CTZW: {
// Only the lower 32 bits of the first operand are read
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index ea98cdb4a1e67..8baae84111a9c 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -168,6 +168,7 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
case RISCV::ROLW:
case RISCV::RORW:
case RISCV::RORIW:
+ case RISCV::CLSW:
case RISCV::CLZW:
case RISCV::CTZW:
case RISCV::CPOPW:
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🪟 Windows x64 Test Results
Failed Tests(click on a test name to see its output) LLVMLLVM.CodeGen/RISCV/riscv-macho.llIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
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This matches what we do for CLZW and other W instructions.